In the communications field, hardware table lookup is completed using a content storage module. The content storage module can be implemented by a ternary content addressable memory (TCAM) chip, or a content addressable memory (CAM). However, a TCAM chip or a CAM chip in a later version uses a communication interface such as a high-speed serial interface protocol (Interlaken Look Aside, Interlaken-LA) interface or a dedicated CAM interface to receive and send a serial data packet. Therefore, an operation request written into the TCAM chip or the CAM chip, data to be written, a key value, and operation response data generated by the TCAM chip or the CAM chip need to be encapsulated as a serial data packet, which then is input or output through the Interlaken-LA interface or the CAM interface. In addition, a TCAM or CAM chip in an earlier version uses a specific parallel bus.
In the prior art, many processors often provide only a Peripheral Component Interconnect (PCI) interface or a peripheral component interconnect express (PCIe) interface instead of the Interlaken-LA interface or the specific CAM interface (such as, X86 series processors and ARM series processors that are widely applied at present).
However, sometimes, a system using an X86 series processor (such as an application security system) needs to use a TCAM or CAM chip to improve table lookup performance. As shown in FIG. 1, according to an implementation method in the prior art, a field-programmable gate array (FPGA) chip 102 is arranged between an X86 series processor 101 and a content storage module 103, the FPGA chip 102 is connected to the X86 series processor 101 using a PCI bus 104 and is connected to the content storage module 103 using a serial bus 105, the X86 series processor 101 communicates with the FPGA chip 102 using the PCI bus 104, and the FPGA chip communicates with the TCAM or CAM chip using the serial bus 105. The FPGA chip 102 converts physical layer data transmitted over the PCI bus 104 to a serial data packet transmitted over the serial bus 105, or converts a serial data packet transmitted over the serial bus 105 to physical layer data transmitted over the PCI bus 104.
In the foregoing solution of the prior art, because the FPGA chip needs to be arranged and logic development work for the FPGA chip is required, an application threshold is higher. In addition, power consumption of the FPGA chip is usually high. Therefore, using the FPGA chip increases power consumption and raises a cost. In addition, because the FPGA chip needs to convert physical layer data transmitted over a PCI bus to a serial data packet, conversion of a data format also results in longer data processing time.